1. Field of the Invention
The present invention relates to a solid electrolytic capacitor array and a method for manufacturing the same. More specifically, the present invention relates to a so-called solid electrolytic capacitor array in which a plurality of capacitor elements each having a sintered unit of valve-metallic powder are arranged in parallel with each other and integrally packaged, and a method for manufacturing such solid electrolytic capacitor arrays.
2. Description of the Prior Art
Examples of such a kind of solid electrolytic capacitor array are disclosed in, for example, FIG. 3 of U.S. Pat. No. 4,097,916 issued on Jun. 27, 1978, Japanese Patent Application Laying-open No.4-3406 issued on Jan. 8, 1992, FIG. 11 of Japanese Patent Application Laying-open No. 6-20891 issued on Jan. 28, 1994, and etc.
Then, there is an advantage in such the solid electrolytic capacitor array that in a case where a plurality of solid electrolytic capacitors are used in a circuit board of an electric equipment, it is possible to reduce the number of steps for mounting the capacitors on the circuit board and a mounting space necessary for mounting the capacitors on the circuit board in comparison with a case where a plurality of solid electrolytic capacitors each having only a single capacitor element are mounted on the circuit board.
Furthermore, in a case of a solid electrolytic capacitor array in which a plurality of capacitor elements are connected in parallel with each other and integrally packaged, it is possible to reduce electric resistance at cathode electrodes of the capacitor elements, and therefore, there is an advantage that impedance in a high-frequency region can be lowered in comparison with a case where a capacitor having the same capacity is constructed by only a single capacitor element.
Each of the prior art solid electrolytic capacitor arrays utilizes a capacitor element A which is manufactured as follows:
First, as shown in FIG. 1, powder of valve-metal such as tantalum are tamped and formed into a porous chip A1 from which an anode wire A2 made of metal such as tantalum is projected, and thereafter, the porous chip A1 is sintered.
Next, as shown in FIG. 2, in a state where the chip A1 is immersed in a chemical conversion liquid such as an aqueous solution of phosphoric acid, a DC current is applied between the anode wire A2 and the chemical conversion liquid so as to perform anodization. Consequently, a dielectric film A3 such as ditantalum pentaoxide is formed on surfaces of the metallic powder or particles in the chip.
Then, a step for firing the chip A1 after the chip A1 is immersed in an aqueous solution of manganese nitrate so as to permeate the manganese nitrate solution into an inside of the chip A1 and pulled-out is repeated a plurality of times. Consequently, a solid electrolytic layer A4 is formed on a surface of the dielectric film A3 by metal oxide such as manganese dioxide.
Lastly, after a graphite layer is formed on a surface of the solid electrolytic layer A4 of the chip A1, a cathode electrode A5 is formed by a metallic film such as silver, nickel, and etc., whereby the capacitor element A can be obtained.
As described above, in the solid electrolytic capacitor, in manufacturing the capacitor element A, the anode wire A2 projected from the chip A1 is indispensable, and therefore, the anode wire A2 can not be eliminated.
Therefore, in the prior art, after a plurality of capacitor elements A each thus manufactured are arranged in parallel with each other, the capacitor elements A are to be integrally molded by a package unit made of synthetic resin in a manner that the package unit covers not only the chips of the capacitor elements but also the anode wires A2 being projected from the chips.
Therefore, a size of the package unit becomes large in comparison with a size of the chip A1 of the capacitor element A by a portion of the anode wire A2 is projected from the chip A1, and therefore, a rate of a volume of the chip A1 of the capacitor element A with respect to a volume of a whole capacitor, and accordingly, a volumetric efficiency becomes low. Furthermore, an effective volume of the chip A1 of the capacitor element A becomes small because a portion of the anode wire A2 is embedded in the chip A1.
For these reasons, in the prior art, there was a problem that it is difficult to make a capacity per unit volume large, and thus, a weight of the capacitor also becomes large.
Furthermore, in the prior art, in molding the plurality of capacitor elements A by the package unit of the synthetic resin, a large stress acts on the chip A1 of the capacitor element A, and therefore, there are much possibilities that a leakage current (LC) increases and an insulation defect occurs. Accordingly, in manufacturing the capacitor, an incidence of inferior products is high, and thus, an yield rate is low.
Furthermore, in the prior art, in a case where the plurality of capacitor elements A are to be simultaneously manufactured, the anode wires A2 which are respectively projected from the plurality of the sintered chips are fit to a metal rod such as tantalum, and in its state, a step for forming the dielectric film A3 by the anodization in the chemical conversion liquid, a step for forming the solid electrolytic layer A4 in the aqueous solution of manganese nitrate, a step for forming the graphite layer, and a step for forming the cathode electrode A5 are performed, and then, respective capacitor elements A are cut-out of the metal rod. Therefore, the number of the capacitor elements A capable of being manufactured with using a single metal rod is limited, and it is impossible to largely increase the number of the capacitor elements A, and therefore, it is difficult to manufacture the capacitor elements by mass-production. Furthermore, it is necessary to provide a step for incorporating a plurality of capacitor elements A thus manufactured in a single component, and therefore, there was a problem that not only an yield rate is low but also a manufacturing cost largely increases.